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Benchmarks and tests were performed on the following system configurations:
Intel PIII-550E @ 770 MHz (5.5x140MHz) /w motherboard (aa)
Intel PIII-450 @ 558 MHz (4.5x124MHz) /w motherboard (bb)
Intel PIII-450 MHz with motherboard (bb)
Epox EP-6VBA2 + OS (VIA Apollo 133A Rev “CE” chipset – UDMA66, AGP4x, PC133)
- Windows 98SE
- VIA AGP mini-port 3.59 + VIA Bus master 2.1.44 drivers
- (bb) Abit BX6-R2 (Intel BX chipset – UDMA 33, AGP2x, PC100)
- (aaa) Matrox Marvel G400-TV + drivers
- PowerDesk for Windows 95/98 Revision 5.30.007
- Video Tools for Windows 95/98 Version 1.51.024
- TurboGL V 1.00.002
- (bbb) Creative GeForce Pro (32MB DDR)
- Reference drivers Version 3.68
- 128 MB Mushkin PC133 SDRAM (Samsung-G6)
- IBM 20GB UDMA66 (IBM-DPTA-372050)
- Seagate 10GB UDMA66 (ST310232 A)
- Creative Soundblaster “Live!” Value Retail (Liveware 3)
CPU utilization traced with Windows System Monitor.
2D Quality and Performance
Matrox have had a history of providing high quality and outstanding performance in 2D – something I am happy to report has not changed with the Marvel. The Windows desktop and icons were crystal clear at all resolutions, even on my normally fussy Viewsonic E771.
2D performance was tops – check out the following benchmark:
Notes: Configuration (a)+(aa) i.e. PIII-550E @ 770MHz, Epox EP-6VBA2 – 1024x768x32bits
The Marvel was right up there, trading punches with the GeForce Pro (the latter with DDR memory and +50MHz RAMDAC advantage), and winning quite a few bouts at that.
Tech Talk: 256-bit Dual Bus Architecture
According to Matrox’s technical paper, contributing to the outstanding 2D performance is the 256-bit dual bus architecture of the G400.
Dual Bus Block Diagram
To put it simply, the G400 has one 128-bit data bus feeding data into the 2D/3D Engine, and a separate 128-bit data bus retrieving the results. Input and output data buffers evens out the speed difference between the external bus speed and the internal bus speed so that there is always data ready to be processed.
Dual Bus vs. traditional single 128-bit bus timing diagrams
The result is 128-bits of valid data on every clock cycle, compared with 128-bits of data every other clock cycles in traditional 128-bit bus designs. This architecture probably contributes to 3D performance to a lesser extent, as the critical path in 3D performance is likely to be the 3D engine rather than the input/output bus.