   ABIT BP6 Dual Socket370 Motherboard - Page 8
 Analysis Remember that Celerons are meant for 66Mhz FSB operations and have 128K on-die caches? So, how good is it in a SMP environment? I mean, is the 128K on-die cache good enough? Furthermore, it's only running on a 66 MHz bus, shared by 2 processors. This means each processor roughly gets only 33Mhz of bus bandwidth to the main memory. Now, compare to its more powerful siblings, the Pentium II and Pentium III. They feature 512K of cache running at half of CPU speed, and they operate on a 100 MHz Front Side Bus. If you compare that with the Xeon, you will see that the Xeon is better off with 512K-2Mb of cache at full speed. System Diagram Now, how does the 66 Mhz and 100 Mhz FSB affect the system? Let me give you an example in theoretical terms: Supposing we have a memory and bus system supporting block access of four 32-bit words. Then we have a 32-bit synchronous bus clocked at 66 Mhz/100 Mhz, with each 32-bit transfer taking 1 clock cycle, and 1 clock cycle is required to send an address to the memory. Two clock cycles are needed between each bus operation (assuming bus is idle before an access). A memory access time for the first four words is 200ns. Each addition set of four words can be read in 20ns. Assume that a bus transfer of the most recently data and a read of the next four words can be overlapped. Then, let us run our own benchmarks to find the sustained bandwidth and latency for a read of 1000 words for transfers that use 4-word blocks.  Let us consider the 66 MHz FSB first: 1 clock cycle is required to send the address to memory 200 ns / (1/66) = 13.2 clock cycles to read memory 2 clock cycles to send data from the memory 2 idle clock cycles between this transfer and the next Hence total clock cycles needed = 18.2 cycles and 1000 / 4 = 250 transactions needed. Therefore, the entire transfer takes 18.2 * 250 = 4550 clock cycles. Therefore, latency is 4550 * (1/66 * 1000) = 68,939 ns. The number of bus transactions per second is 250 * 1 s/68939 ns = 3.62M transactions/second  Hence bus bandwidth is: (1000 x 4) bytes x 1 s/68939 ns = 58.02 MB/sec Considering the 100 MHz FSB: 1 clock cycle is required to send the address to memory 200 ns / (1/100) = 20 clock cycles to read memory 2 clock cycles to send data from the memory 2 idle clock cycles between this transfer and the next Total clock cycles needed = 25 cycles and 250 transactions are needed. Entire transfer takes 25 * 250 = 6250 clock cycles. Therefore, latency is 6250 * 10 ns  = 62,500 ns.  250 * 1 s/62500 ns = 4M transactions/second Hence bus bandwidth is: (1000 x 4) bytes x 1 s / 62500 = 64 MB/sec So, according to the 'theoretical results', the difference between the 66 and 100 MHz bus is only 10%. This is for the same processor speed in both 66 MHz and 100 Mhz system (which isn't really possible to test in real-life as Intel locked their processors).  It's pretty interesting what real figures show according to the specifications. No fanciful Winstone results or anything like that. The advantages of a 100 Mhz FSB is clear. I will recommend you to get a BP6 if you can secure two Celerons which are capable of operating at clockspeeds using a 100 Mhz FSB. They should fly!
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